The present invention relates to a data processor and, in particular, to a central processing unit (CPU) such as a microcomputer or microcontroller. Microcontrollers are well known in the art, and a large variety of such devices from low end devices (e.g., a 4/8-bit controller) to high end devices (e.g., a 32-bit controller) are available. High end controllers are used in almost any kind of electronic devices, such as laser printers and hard disks or for controlling any kind of processes, for example, in automobiles, etc.
With more complex tasks to be solved, the demand for very fast, high end controllers is rising. In particular, such devices are necessary to control real time applications. In such applications, it is necessary to process data very fast. It is known in the art of microcomputers and microcontrollers to use the so called pipeline technique to speed up data processing. It is also known to use multiple pipelines in parallel to process data even faster.
A highly parallel and pipelined computer processor, for example, is a very long instruction word (VLIW) processor as disclosed in U.S. Pat. No. 5,450,556. Such a VLIW processor has a plurality of arithmetic and logic units which process instruction in parallel to speed up the operation of the computer. Therefore, a multi-port register file is connected to a plurality of units as shown in FIG. 1 of the above mentioned disclosure. To process all instructions which are issued in parallel to the respective units correctly a number of precautions, for example dependency checks, completion analysis, resource checks, etc., have to be taken. In VLIW machines, these precautions are mostly shifted to the software side, and they produce lots of code size due to their hardware concept.
Another example for high speed microprocessors or microcontrollers are superscalar machines. Their multiple pipeline design requires, for example a dependency analysis to assure whether instructions issued in parallel are dependent on each other. Also, so called register renaming might be necessary if two instructions read from to the same register. To get the optimal performance it is often necessary to execute instructions out of order, which has to be checked in order not to violate a program order. To support instruction look ahead and internal data forwarding, which are needed to schedule instructions through the multiple pipelines simultaneously so called reservation stations and reorder buffers are necessary. All these precautions and others result in an either very complicate structure including additional hardware and/or in compilers which are able to analyze a program and issue the respective optimized assembler code. These precautions are cumbersome and increase the price of a microcontroller and/or its tools.